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HC55171
Data Sheet July 1998 File Number
4323.4
5 REN Ringing SLIC for ISDN Modem/TA and WLL
The HC55171 is backward compatible to the HC5517 with the added capability of driving 5 REN loads. The HC55171 is ideal for any modem or remote networking access application that requires plain old telephone service POTS, capability. The linear amplifier design allows a choice of Sinusoidal, Square wave or Trapezoidal ringing. The voltage feed architecture eliminates the need for a high current gain node achieving improved system noise immunity, an advantage in highly integrated systems. The device is manufactured in a high voltage Dielectric Isolation (DI) process with an operating voltage range from -16V, for off-hook operation and -80V for ring signal injection. The DI process provides substrate latch up immunity, resulting in a robust system design.
Features
* 5 REN Thru SLIC Ringing Capability to 75VPEAK * Trapezoid, Square and Sinusoid Ringing Capability * Bellcore Compliant Ringing Voltage Levels * Lowest Component Count Trapezoidal Solution * Single Additional +5V Supply * Pin For Pin Compatible With HC5517 * DI Provides Latch-Up Immunity
Applications
* ISDN Internal/External Modems * ISDN Terminal Adapters/Routers * Wireless Local Loop Subscriber Terminals * Cable Telephony Set-Top Boxes * Digital Added Main Line
Ordering Information
PART NUMBER HC55171IM HC55171CM HC55171IB HC55171CB TEMP. RANGE (oC) -40 to 85 0 to 75 -40 to 85 0 to 75 PACKAGE 28 Ld PLCC 28 Ld PLCC 28 Ld SOIC 28 Ld SOIC PKG. NO. N28.45 N28.45 M28.3 M28.3
* Integrated LAN/PBX * Related Literature - AN9606, Operation of the HC5517/171 Evaluation Board - AN9607, Impedance Matching Design Equations - AN9628, AC Voltage Gain - AN9608, Implementing Pulse Metering - AN9636, Implementing an Analog Port for ISDN Using the HC5517 - AN549, The HC-5502X/4X Telephone Subscriber Line Interface Circuits (SLIC)
Block Diagram
TIP FEED TIP SENSE 2-WIRE INTERFACE 4-WIRE INTERFACE VRX VTX VRING + - IN 1 OUT 1
RING FEED RING SENSE 1 RING SENSE 2 VREF RTI VBAT VCC
LOOP CURRENT DETECTOR FAULT DETECTOR CURRENT LIMIT RING TRIP DETECTOR
SHD ALM ILMT RTD RELAY DRIVER RDI RDO
BIAS AGND BGND F1 F0 RS TST IIL LOGIC INTERFACE
62
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HC55171
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC, PLCC - Lead Tips Only)
Maximum Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V VCC - VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V
Operating Conditions
Temperature Range HC55171IM, HC55171IB . . . . . . . . . . . . . . . . . . . . -40oC to 85oC HC55171CM, HC55171CB . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V Positive Power Supply, VCC . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% Negative Power Supply, VBAT . . . . . . . . . . . . . . . . . . . .-16V to -80V
Die Characteristics
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 x 144 Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VBAT Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600 2-Wire terminating impedance. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER RINGING TRANSMISSION PARAMETERS VRING Input Impedance 4-Wire to 2-Wire Gain AC TRANSMISSION PARAMETERS RX Input Impedance OUT1 Positive Output Voltage Swing OUT1 Negative Output Voltage Swing 4-Wire Input Overload Level (Note 2)
-
5.4 40
-
k V/V
VRING to VT-R (Note 2)
300Hz to 3.4kHz (Note 2) RL = 10k (Note 2) RL = 10k (Note 2) 300Hz to 3.4kHz RL = 1200, 600 Reference (Note 2) Matched for 600, f = 300Hz (Note 2) Matched for 600, f = 1000Hz (Note 2) Matched for 600, f = 3400Hz (Note 2)
+2.5 -4.5 -
108 +3.1
-
k V V VPEAK dB dB dB dB
2-Wire Return Loss
37 40 30 58
63
-
2-Wire Longitudinal to Metallic Balance Off Hook 4-Wire Longitudinal Balance Off Hook Longitudinal Current Capability Insertion Loss, 2W-4W Insertion Loss, 4W-2W Insertion Loss, 4W-4W Frequency Response
Per ANSI/IEEE STD 455-1976 300Hz to 3400Hz (Note 2) 300Hz to 3400Hz (Note 2) ILINE = 40mA, TA = 25oC (Note 2) 0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3 0dBmO,1kHz 0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3 300Hz to 3400Hz Referenced to Absolute Level at 1kHz, 0dBm Referenced 600
-
55 40 0.05 0.05 0.02
0.2 0.2 0.25 0.06
dB mARMS dB dB dB dB
63
HC55171
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600 2-Wire terminating impedance. (Continued) TEST CONDITIONS +3 to 0dBm, Referenced to -10dBm (Note 2) 0 to -40dBm, Referenced to -10dBm (Note 2) -40 to -55dBm, Referenced to -10dBm (Note 2) Absolute Delay, 2W-4W Absolute Delay, 4W-2W Absolute Delay, 4W-4W Transhybrid Loss Total Harmonic Distortion 2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire Idle Channel Noise 2-Wire and 4-Wire PSRR, VCC to 2W PSRR, VCC to 4W PSRR, VBAT to 2W PSRR, VBAT to 4W PSRR, VCC to 2W PSRR, VCC to 4W PSRR, VBAT to 2W PSRR, VBAT to 4W PSRR, VCC to 2W PSRR, VCC to 4W PSRR, VBAT to 2W PSRR, VBAT to 4W DC PARAMETERS Loop Current Programming Range Loop Current Programming Accuracy Loop Current During Power Denial Fault Current, Tip to Ground Fault Current, Ring to Ground Fault Current, Tip and Ring to Ground Switch Hook Detection Threshold Ring Trip Comparator Voltage Threshold Thermal ALARM Output Safe Operating Die Temperature Exceeded (Note 2) (Note 2) (Note 2) RL = 200, VBAT = -48V (Note 2) (Note 3) 20 -10 9 -0.28 4 90 100 130 12 -0.24 160 60 +10 15 -0.22 mA % mA mA mA mA mA V
oC
PARAMETER Level Linearity
MIN 36 -
TYP 0.95 40 -
MAX 0.10 0.12 0.30 1.0 1.0 -50
UNITS dB dB dB s s s dB dB
300Hz to 3400Hz (Note 2) 300Hz to 3400Hz (Note 2) 300Hz to 3400Hz (Note 2) VIN = 1VP-P at 1kH (Note 2) Reference Level 0dBm at 600 300Hz to 3400Hz (Note 2) C-Message (Note 2) Psophometric (Note 2) 30Hz to 200Hz, RL = 600 (Note 2)
30 45 23 33
3 -87 35 47 28 38 35 46 50 60 34 40 40 50
-
dBrnC dBmp dB dB dB dB dB dB dB dB dB dB dB dB
200Hz to 3.4kHz, RL = 600 (Note 2)
33 44 40 50
3.4kHz to 16kHz, RL = 600 (Note 2)
30 35 30 40
Dial Pulse Distortion
-
0.1
0.5
ms
64
HC55171
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are over Operating Temperature Range, VBAT = -24V, VCC = +5V, AGND = BGND = 0V. All AC Parameters are specified at 600 2-Wire terminating impedance. (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER UNCOMMITTED RELAY DRIVER On Voltage, VOL Off Leakage Current TTL/CMOS LOGIC INPUTS (F0, F1, RS, TST, RDI) Logic Low Input Voltage Logic High Input Voltage Input Current Input Current LOGIC OUTPUTS (SHD, RTD, ALM) Logic Low Output Voltage Logic High Output Voltage POWER DISSIPATION Power Dissipation On Hook
IOL (RDO) = 30mA
-
0.2 10
0.5 100
V A
0 2.0 IIH , 0V VIN 5V IIL , 0V VIN 5V -
-
0.8 5.5 -1 -100
V V A A
ILOAD = 800A ILOAD = 40A
2.7 -
0.1 300 150 280
0.5 5.5 -
V V
VCC = +5V, VBAT = -80V, RLOOP = VCC = +5V, VBAT = -48V, RLOOP =

-
mW mW mW
Power Dissipation Off Hook
VCC = +5V, VBAT = -24V, RLOOP = 600, IL = 25mA VCC = +5V, VBAT = -80V, RLOOP = VCC = +5V, VBAT = -48V, RLOOP = VCC = +5V, VBAT = -24V, RLOOP =
ICC

-
3 2 1.9 3.6 2.6 2.3
6 5 5 7 6 4.5
mA mA mA mA mA mA
IBAT
VCC = +5V, VB- = -80V, RLOOP = VCC = +5V, VB- = -48V, RLOOP = VCC = +5V, VB- = -24V, RLOOP =

NOTES: 2. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 3. This parameter directly affects device junction temperature. Refer to Power Dissipation discussion of data sheet for design information.
65
HC55171 Functional Diagram
R TF R VRX 17 OUT 1 12 -IN 1 13 VRING 24 VTX 19 VCC 2 BIAS NETWORK AGND 1 22
TF
25
+
R R/2 +2V R/20 R R 2R
BGND
+
OP AMP
27 4 5
VBAT
F1 F0 RS TST
4.5K 100K RING SENSE 1 RING SENSE 2 15 100K 100K 16 100K 4.5K 90K 25K RA RTD
THERM LTD
TSD
IIL LOGIC INTERFACE
TIP SENSE
14
R R
+ 2R
-
TA SHD SH
6 9
GK
+
25K
FAULT DET RFC
7 8 10
SHD RTD ALM RDO
90K 26 RF
RF
+
-
90K
GM VB/2 REF 18 NU 28 RTI
+
-
RF2
21
R = 108k
3 VREF
11 ILMT
20 RDI
HC55171 DEVICE TRUTH TABLE F1 0 0 1 1 F0 0 1 0 1 STATE Loop power Denial Active Power Down Latch RESET, Power on RESET RD Active Normal Loop feed
Power Dissipation Careful thermal design is required to guarantee that the maximum junction temperature of 150oC of the device is not exceeded. The junction temperature of the SLIC can be calculated using:
T J = T A + JA ( I CC V CC + I BAT V BAT - ( ( I LOOP ) * R LOOP ) ) (EQ. 1)
2
The truth table for the internal logic of the HC55171 is provided in the above table. This family of ringing SLICS can be configured to support traditional unbalanced ringing and thru SLIC balanced ringing. Refer to the HC5509A1R3060 for unbalanced ringing application information. The device operating states used by thru SLIC ringing applications are loop power denial and normal feed. During loop power denial, the tip and ring amplifiers are disabled (high impedance) and the DC voltage of each amplifier approaches ground. The SLIC will not provide current to the subscriber loop during this mode and will not detect loop closure. Voice transmission occurs during the normal loop feed mode. During normal loop feed the SLIC is completely operational and performs all transmission and supervisory functions.
Where TA is maximum ambient temperature and JA is junction to air thermal resistance (and is package dependent). The entire term in parentheses yields the SLIC power dissipation. The power dissipation of the subscriber loop does not contribute to device junction temperature and is subtracted from the power dissipation term. Operating at 85oC, the maximum PLCC SLIC power dissipation is 1.18W. Likewise, the maximum SOIC SLIC power dissipation is 0.92W.
66
HC55171
Circuit Operation and Design Information
Introduction
The HC55171 is a high voltage Subscriber Line Interface Circuit (SLIC) specifically designed for through SLIC ringing applications. Through SLIC ringing applications are broadly defined as any application that requires ringing capability but does not have the standard wired central office interface. The most common implementation of the ringing SLIC is in the analog pots port. The analog pots port provides the ringing function as well as interface compatibility with answering and fax machines. Full Duplex Analog Transmission Familiarity with the signal paths of the SLIC is critical in understanding the full duplex transmission capability of the device. The analog interfaces of the SLIC are categorized as 2-wire interfaces and 4-wire interfaces. The 2-wire interface of the SLIC consists of the bidirectional Tip and Ring terminals of the device. A differential transmitter drives AC signals out of the Tip and Ring terminals to the handset. A differential receiver across Tip and Ring receives AC signals from the handset. The differential receiver is connected across sense resistors that are in the Tip and Ring signal paths. The differential transmitter and receiver concept is depicted in Figure 2.
Subscriber Line Interface Basics
The basic SLIC provides DC loop current to power the handset, supports full duplex analog transmission between the handset and CODEC, matches the impedance of the SLIC to the impedance of the handset and performs loop supervision functions to detect when the handset is off hook. The ringing SLIC adds through the SLIC ringing capability to this suite of features. The analog interfaces of the SLIC are categorized as the 2-wire interface (high voltage DC, differential AC) and the 4-wire interface (low voltage DC, single ended AC). DC Loop Current The Tip and Ring terminals of the subscriber line circuit are biased at negative potentials with respect to ground. The Tip terminal DC potential is slightly negative with respect to ground, and the ring terminal DC potential is slightly positive with respect to the battery voltage (resulting in a large negative voltage). The HC55171 typical Tip DC voltage is -4V and the typical ring DC voltage is defined as VBAT + 4V. For example, when the battery voltage is -24V the ring voltage is -20V. To clearly comprehend the Tip and Ring interface it is helpful to understand that the handset and the SLIC constitute a DC and AC current loop as shown in Figure 1. The loop is often referred to as the subscriber loop.
DIFFERENTIAL TRANSMITTER -1
-
+
+
+ DIFFERENTIAL RECEIVER
FIGURE 2. DIFFERENTIAL TRANSMIT/RECEIVE CONCEPT
Since the receiver is connected across the transmit signal path, one may deduce that in addition to receiving signals from the handset, the receiver will detect part of the transmit signal. Indeed this does occur and is the reason that all SLIC circuits require a hybrid balance or echo cancellation function. The 4-wire interface of the SLIC consists of the receive (VRX) and transmit (OUT1) terminals. The 4-wire interfaces are single ended signal paths. The receiver is a dedicated input port and the transmitter is a dedicated output port. The 4-wire receive input of the SLIC drives the 2-wire differential transmitter and the 2-wire differential receiver drives the 4wire transmit output. The complete signal path for voice signals includes two digital data busses, a CODEC and a SLIC. There is a receive data bus and transmit data bus, each with an independent 3wire serial interface. The CODEC contains a coder and decoder. The coder converts the SLIC analog transmit output to digital data for the transmit data bus. The receive digital data bus is converted to analog data and drives the SLIC receive input. The CODECs use logarithmic compression schemes to extend the resolution of the 8-bit data to 14 bits. The accepted compression schemes are A-law (Intersil CODEC CD22357A) and -law (Intersil CODEC - CD22354A). The complete signal path from the handset to the CODEC is shown in Figure 3.
TIP LOOP CURRENT RING SLIC
FIGURE 1. SUBSCRIBER LOOP
When the handset is on hook (idle) the phone is an open circuit load and the DC loop current is zero. The SLIC can still provide AC transmission in this condition, which supports caller id services. The DC resistance of the off hook handset is typically 400. Since the Tip DC voltage is more positive than the ring DC voltage, DC loop current flows from Tip to Ring when the handset is off hook. The SLIC is designed with feedback to limit the maximum loop current when the handset is off hook.
67
HC55171
LOAD IMPEDANCE RSYNTH TIP VRX RX OUT TX IN PCM IN RP RS TIP
SLIC
CODEC
OUT1 RING
RING PCM OUT DIGITAL RP RS RSYNTH SLIC SOURCE IMPEDANCE -1
ANALOG
FIGURE 3. COMPLETE VOICE SIGNAL PATH
FIGURE 4. SLIC IMPEDANCE DIAGRAM
Impedance Matching Impedance matching is used to match the AC source impedance of the SLIC to the AC source impedance of the load. When the impedance is matched, the voltage level at the receive input of the SLIC will be the same voltage level that is at the 2-wire differential output (i.e., Tip and Ring). Impedance matching applies only to the 2-wire interface, not the 4-wire interface. Slic AC signal power levels are most commonly assigned the units dBmO. The term dBmO refers to milliwatts in a 600 load. The typical AC power level is 0dBmO which is 1mW referenced to a 600 load. The relationship between dBmO and VRMS is provided in Equation 2.
( V RMS ) dBmO = 10 log 1000 ----------------------- 600
2
showing the impedance terms is shown in Figure 4. Loop Supervision The SLIC must detect when the subscriber picks up the handset when the SLIC is not ringing the phone and when the SLIC is ringing the phone. The HC55171 uses a switch hook detector output to indicate loop closure when the SLIC is not ringing the phone. When the SLIC is ringing the phone, loop closure is indicated by the ring trip detector. (Recall from earlier discussions that the subscriber loop is open when the handset is on hook and closed when off hook. The DC impedance of the handset when off hook is typically 400.) When the handset is off hook, DC loop current flows from Tip to Ring and the transmit output voltage increases to a negative value. In addition to interfacing to the CODEC and providing the feedback for impedance matching, the transmit output also drives the input to a voltage comparator. When the comparator threshold is exceeded, the SHD output goes to a logic low, indicating the handset is off hook. When the call is terminated and the handset is returned on hook, the transmit voltage decreases to zero, crossing the comparator threshold and setting SHD to a logic high. Loop closure must also be detected when the SLIC is ringing the handset. The balanced ringing output of the SLIC coincides with a zero DC potential between Tip and Ring. Therefore the ring trip must be designed around an AC only waveform at the transmit output. When the SLIC is ringing and the handset is on hook, the echo of the ringing signal is at the transmit output. When the handset goes off hook, the amplitude of the ringing echo increases. The increase in amplitude is detected by an envelope detector. When the echo increases, the envelope detector output increases and exceeds the ring trip comparator threshold. Then RTD goes to a logic low, indicating the handset is off hook. When the system controller detects a logic low on RTD, the ringing is turned off and the Tip and Ring terminals return to their typical negative DC potentials.
(EQ. 2)
Substituting 0dBmO into the equation should result in 0.7746 VRMS . For sinusoidal signals, multiply the RMS voltage by 1.414 to obtain the peak sinusoidal voltage. The SLIC impedance matching is achieved by applying a feed back loop from the transmit output of the SLIC to the receive input of the SLIC. The transmit output voltage of the HC55171 is proportional to the loop current (DC + AC) flowing in the subscriber loop. The impedance matching feedback only uses the AC portion of the transmit output voltage. Applying a voltage gain to the feedback term and injecting it into the receive signal path, will cause the SLIC to "synthesize" a source impedance that is nonzero. Recall that the impedance matching sets the SLIC source impedance equal to the load impedance. The SLIC application circuit requires external sense resistors in the Tip and Ring signal paths to achieve the differential receive function. The sense resistors contribute to the source impedance of the SLIC and are accounted for in the design equations. Specifically, if the load impedance is 600 and each sense resistor is 50, the SLIC must synthesize an additional source impedance of 500 (i.e., 600 - 2(50)). In addition to the sense resistors, some applications may use a protection resistor in each of the Tip and Ring leads as part of a surge protection network. These resistors also contribute to the SLIC source impedance and can be easily accounted for in the design equations. If 50 protection resistors are added to the prior example, the SLIC would then have to synthesize 400 to match the load (i.e., 600 - 2(50) - 2(50)). A diagram
Design Equations and Operational Theory
The following discussion separates the SLICS's operation into its DC and AC path, then follows up with additional circuit design and application information.
68
HC55171 DC Operation of Tip and Ring Amplifiers
SLIC in the Active Mode The tip and ring amplifiers are voltage feedback op amps that are connected to generate a differential output (e.g., if tip sources 20mA then ring sinks 20mA). Figure 5 shows the connection of the tip and ring amplifiers. The tip DC voltage is set by an internal +2V reference, resulting in -4V at the output. The ring DC voltage is set by the tip DC output voltage and an internal VBAT/2 reference, resulting in VBAT +4V at the output. (See Equation 3, Equation 4 and Equation 5.)
R V TIPFEED = V C = - 2V ---------- = - 4V R 2 V BAT R R V RINGFEED = V D = -------------- 1 + --- - V TIPFEED --- R 2 R V RINGFEED = V D = V BAT + 4
VRX
Current Limit The tip feed to ring feed voltage (Equation 3 minus Equation 5) is equal to the battery voltage minus 8V. Thus, with a 48 (24) volt battery and a 600 loop resistance, including the feed resistors, the loop current would be 66.6mA (26.6mA). On short loops the line resistance often approaches zero and there is a need to control the maximum DC loop current. Current limiting is achieved by a feedback network (Figure 5) that modifies the ring feed voltage (VD) as a function of the loop current. The output of the Transversal Amplifier (TA) has a DC voltage that is directly proportional to the loop current. This voltage is scaled by RIL1 and RIL2 . The scaled voltage is the input to a transconductance amplifier (GM) that compares it to an internal reference level. When the scaled voltage exceeds the internal reference level, the transconductance amplifier sources current. This current charges CIL in the positive direction causing the ring feed voltage (VD) to approach the tip feed voltage (VC). This effectively reduces the tip feed to ring feed voltage (VT-R). and holds the maximum loop current constant. The maximum loop current is programed by resistors RIL1 and RIL2 as shown in Equation 7 (Note: RIL1 is typically 100k).
( 0.6 ) ( R IL1 + R IL2 ) I LIMIT = ------------------------------------------------( 200xR IL2 ) (EQ. 7)
(EQ. 3)
(EQ. 4)
(EQ. 5)
R R TIP FEED TIP RP1 RS1 + V +C TRANSVERSAL AMP TA + RIL1 R
OUT1 R/20 VRING R/2 + INTERNAL - +2V REF VTX
-
-
-
0 VTIP FEED = -4V TIP AND RING VOLTAGE (V) -5 CONSTANT VOLTAGE REGION -10
+ RIL2 90k RING FEED RING RP2 RS2 + + VOUT1, VRX GROUNDED FOR DC ANALYSIS 90k RF2
-
GM
-15 VRING FEED = -20V -20 CURRENT LIMIT REGION ILOOP = 25mA 0 250 500 750 LOOP RESISTANCE ()
-
90k CIL +
- VD
-
VBAT 2
-25
FIGURE 5. OPERATION OF THE TIP AND RING AMPLIFIERS FIGURE 6. VT-R vs RL (VBAT = -24V, ILIMIT = 25mA)
Transmit Output Voltage The transmit output voltage in terms of loop current is expressed as 200x ILOOP. The 200 term is actually formed by the sum of twice the sense resistors and is shown in the following equation.
200 x I LOOP = ( 2 R S1 + 2 R S2 ) x I LOOP (EQ. 6)
This is a relationship that is critical when modifying the sense resistor (RS1, RS2). The 200 term factors into the loop current limit and loop detector functions of the SLIC.
Figure 6 illustrates the relationship between VT-R and the loop resistance. The conditions are shown for a battery voltage of -24V and the loop current limit set to 25mA. For an open circuit loop the tip feed and ring feed are at -4V and -20V respectively. When the loop resistance decreases from infinity to about 640 the loop current (obeying Ohm's Law) increases from 0mA to the set loop current limit. As the loop resistance continues to decrease, the ring feed voltage approaches the tip feed voltage as a function of the programmed loop current limit (Equation 7).
69
HC55171 AC Voltage Gain Design Equations
The HC55171 uses feedback to synthesize the impedance at the 2-wire tip and ring terminals. This feedback network defines the AC voltage gains for the SLIC. The 4-wire to 2-wire voltage gain (VRX to VTR) is set by the feedback loop shown in Figure 7. The feedback loop senses the loop current through resistors RS1 and RS2 , sums their voltage drop and multiplies it by 2 to produce an output voltage at the VTX pin equal to +4RSIL . The VTX voltage is then fed into the -IN1 input of the SLIC's internal op amp. This signal is multiplied by the ratio RZ0/RRF and fed into the tip current summing node via the OUT1 pin. (Note: the internal VBAT/2 reference (ring feed amplifier) and the internal +2V reference (tip feed amplifier) are grounded for the AC analysis.) The current into the summing node of TF amp is equal to:
4R S I L R Z0 I OUT1 = - -------------------- ----------- R R RF (EQ. 8) R Z0 2 x - 4 R S I L ----------- + V RX R RF I L = ----------------------------------------------------------------------------R L + R P1 + R P2 + R S1 + R S2
(EQ. 15)
Equation 15 simplifies to
2V RX - 400 I L I L = --------------------------------------800 (EQ. 16)
Solving for IL results in
V RX I L = ----------600 (EQ. 17)
Equation 17 is the loop current with respect to the feedback network. From this, the 4-wire to 2-wire and the 2-wire to 4-wire AC voltage gains are calculated. Equation 18 shows the 4-wire to 2-wire AC voltage gain is equal to 1.00.
V RX ----------- ( 600 ) V TR I L ( R L ) 600 A 4W - 2W = ----------- = -------------------- = -------------------------- = 1 V RX V RX V RX (EQ. 18)
Equation 9 is the node equation for the tip amplifier summing node. The current in the tip feedback resistor (IR) is given in Equation 7.
4R S I L R Z0 V RX - I R - -------------------- ----------- + ----------- = 0 R R RF R 4R S I L R Z0 V RX I R = - -------------------- ----------- + ----------R R RF R (EQ. 9)
Equation 19 shows the 2-wire to 4-wire AC voltage gain is equal to -0.333.
R Z0 V RX - 4 R S I L ----------- - 200 ----------- ( 1 ) V OUT1 R RF 600 1 A 2W - 4W = ------------------ = ----------------------------------------- = --------------------------------- = - -I L ( R L ) V TR V RX 3 ----------- ( 600 ) 600 (EQ. 19)
(EQ. 10)
The AC voltage at VC is then equal to:
VC = ( IR ) ( R ) R Z0 V C = - 4 R S I L ----------- + V RX R RF (EQ. 11)
Impedance Matching
The feedback network, described above, is capable of synthesizing both resistive and complex loads. Matching the SLIC's 2-wire impedance to the load is important to maximize power transfer and maximize the 2-wire return loss. The 2-wire return loss is a measure of the similarity of the impedance of a transmission line (tip and ring) and the impedance at it's termination. It is a ratio, expressed in decibels, of the power of the outgoing signal to the power of the signal reflected back from an impedance discontinuity. Requirements for Impedance Matching Impedance matching of the HC55171 application circuit to the transmission line requires that the impedance be matched to points "A" and "B" in Figure 7. To do this, the sense and protection resistors RP1 , RP2 , RS1 and RS2 must be accounted for by the feedback network to make it appear as if the output of the tip and ring amplifiers are at points "A" and "B". The feedback network takes a voltage that is equal to the voltage drop across the sense resistors and feeds it into the summing node of the tip amplifier. The effect of this is to cause the tip feed voltage to become more negative by a value that is proportional to the voltage drop across the sense resistors RP1 and RS1. At the same time the ring amplifier becomes more positive by the same amount to account for resistors RP2 and RS2 . The net effect cancels out the voltage drop across the feed resistors. By nullifying the effects of the feed resistors the
(EQ. 12)
and the AC voltage at VD is:
R Z0 V D = 4R S I L ----------- - V RX R RF (EQ. 13)
The values for RZ0 and RRF are selected to match the impedance requirements on tip and ring, for more information refer to AN9607 "Impedance Matching Design Equations for the HC5509 Series of SLICs". The following loop current calculations will assume the proper RZ0 and RRF values for matching a 600 load. The loop current (IL) with respect to the feedback network, is calculated in Equations 14 through 17. Where RZ0 = 40k, RRF = 40k, RL = 600, RP1 = RP2 = RS1 = RS1 = 50.
VC - VD I L = ----------------------------------------------------------------------------R L + R P1 + R P2 + R S1 + R S2 (EQ. 14)
Substituting the expressions for VC and VD
70
HC55171
feedback circuitry becomes relatively easy to match the impedance at points "A" and "B". Impedance Matching Design Equations Matching the impedance of the SLIC to the load is accomplished by writing a loop equation starting at VD and going around the loop to VC . The loop equation to match the impedance of any load is as follows (note: VRX = 0 for this analysis):
R Z0 R Z0 - 4R S I L ----------- + 2R S I L - V IN + R L I L + 2R S I L - 4R S I L ----------- R RF R RF (EQ. 20) R Z0 V IN = - 8R S I L ----------- + 4R S I L + R L I L R RF R Z0 V IN = I L - 8R S ----------- + 4R S + R L R RF
VIN + RL LOAD SLIC R Z0 8RS ------------ + 4R S R RF
FIGURE 8. SCHEMATIC REPRESENTATION OF EQUATION 20
The result is shown in Equation 23. Figure 8 is a schematic representation of Equation 18. To match the impedance of the SLIC to the impedance of the load, set:
R Z0 8R S ----------- + 4R S = R L R RF (EQ. 24)
(EQ. 21)
If RRF is made to equal 8RS then:
R Z0 + 4R S = R L (EQ. 25)
(EQ. 22)
Therefore to match the HC5517, with RS equal to 50, to a 600 load:
R RF = 8R S = 8 ( 50 ) = 400 (EQ. 26)
Equation 22 can be separated into two terms, the feedback (-8RS(RZ0/RRF)) and the loop impedance (+4RS+RL).
V IN R Z0 ------------ = - 8 R S ----------- + [ 4R S + R L ] I L R RF (EQ. 23)
and
R Z0 = R L - 4 R S = 600 - 200 = 400 (EQ. 27)
To prevent loading of the VTX output, the value of RZ0 and RRF are typically scaled by a factor of 100:
KR Z0 = 40k
R IR R R
KR RF = 40k
(EQ. 28)
- 4 ( R S I L ) R V Z0 RX I R = ----------------------------- ------------ + -----------R R R RF + IL RP1 TIP + VC
Since the impedance matching is a function of the voltage gain, scaling of the resistors to achieve a standard value is recommended. For complex impedances the above analysis is the same.
-
+ IL RS1
R/20
+
-
Reactive ( KR RF = 40k ) KR Z0 = 100 ( Resistive - 200 ) + ------------------------- 100 (EQ. 29)
R/2
-
A
VC = -4 RS
Refer to application note AN9607 ("Impedance Matching Design Equations for the HC5509 Series of SLICs") for the values of KRRF and KRZ0 for many worldwide typical line impedances.
VTR RL IL + RP1 = RP2 = RS1 = RS2 = RS
Through SLIC Ringing
The HC55171 uses linear amplification to produce the ringing signal. As a result the ringing SLIC can produce sinusoid, trapezoid or square wave ringing signals. Regardless of the wave shape, the ringing signal is balanced. The balanced waveform is another way of saying that the tip and ring DC potentials are the same during ringing. The following figure shows the Tip and Ring waveforms for sinusoid and trapezoid wave shapes as can be displayed using an oscilloscope. Pertinent Bellcore Ringing Specifications Bellcore has defined bounds around the existing unbalanced ringing signal that is supplied by the central office. The
VIN + -
IL + B RP2 RING RS2 90k 90k
+
-
-
IL +
-
IL +
+
- VD
V D = 4R S
FIGURE 7. AC VOLTAGE GAI
71
HC55171
GROUND TIP
circuit published in the HC5517 and HC55171 data sheet.
TABLE 1. RING TRIP COMPONENT DIFFERENCES COMPONENT R15
RING
HC5517 47k 56.2k 1.0F
COMPONENT RRT3 RRT1 CRT
HC55171 51.1k 49.9k 0.47F
R17 C10
BATTERY (A) SINUSOID GROUND TIP
The sinusoidal circuit published in the HC5517 can be used as an additional reference circuit for the HC55171. To generate a sinusoid ringing signal, two conditions must be met on the ringing (VRING) input of the SLIC. The first condition is that a positive DC voltage, which is directly related to the battery voltage, must be present at the ringing input. The DC voltage is used to force the Tip and Ring DC outputs to half the battery voltage. Having both the Tip and Ring amplifiers biased at the same DC voltage during ringing is one characteristic of balanced ringing. The centering voltage (VC) can be calculated from the following equation.
V BAT V C = -------------- - 4 20 2 (EQ. 30)
RING BATTERY (B) TRAPEZOID
FIGURE 9. BALANCED RINGING WAVESHAPES
HC55171 ringing SLIC meets the REN drive requirement, the crest factor limitations and the minimum RMS ringing voltage. The foremost requirement is that the ringing source must be able to drive 5 REN. A REN is a ringer equivalence number modeled by a 6.93k resistor in series with a 8F capacitor (see Figure 10). The impedance of 1 REN at 20Hz is approximately 7k. 5 REN is equivalent to five of the networks in parallel. Figure 10 provides the Bellcore REN models. The crest factor of the ringing waveform is the ratio of the peak voltage to the RMS voltage. For reference, the crest factor of a sinusoid is 1.414 and of a square wave is 1.0. Bellcore defines the crest factor range from 1.2 to 1.6. A signal with a crest factor between 1.2 and 1.414 resembles the trapezoid of Figure 9. A signal with a crest factor between 1.414 and 1.6 resembles a "rounded triangular" wave shape and is an inefficient waveform for the ringing SLIC.
40F 1386 5 REN 8F 6930 1 REN
Substituting values of battery voltage, the centering voltage is +1.8V for a -80V battery and +1.3V for a -60V battery. The second condition that must be met for sinusoidal ringing is a low level ringing signal must be applied to the ringing input of the SLIC. The AC signal that is present at VRING will be amplified by a gain of 20 through the Tip amplifier and a then inverted through the ring amplifier, resulting in a differential gain of 40. The maximum low level amplitude that can be injected for a given battery voltage can be determined from the following equation.
V RING ( Max ) = ( V BAT - 8 ) 20 (EQ. 31)
The maximum output swing may be increased by driving the VRING negative by 200mV. Equation 31 can then by rewritten as:
V RING ( Max ) = ( V BAT - 5 ) 20 (EQ. 32)
FIGURE 10. BELLCORE RINGER EQUIVALENCE MODELS
The third pertinent Bellcore requirement is the that RMS ringing voltage must be greater than 40VRMS at the telephone instrument. The HC5517 is able to deliver 40VRMS at the end of 500 loops. The 500 loop drive capability of the HC5517 is achieved with trapezoidal ringing.
Exceeding the maximum signal calculated from the above equation will cause the peaks of the sinusoid to clip at ground and battery. The compression will reduce the crest factor of the waveform, producing a trapezoidal waveform. This is just one method, though inefficient, for achieving trapezoidal ringing. The application circuit provided with the HC55171 has been specifically developed for trapezoidal ringing and may also be used with the HC5517.
Trapezoidal Ringing
The trapezoidal ringing waveform provides a larger RMS voltage to the handset. Larger RMS voltages to the handset provide more power for ringing and also increase the loop length supported by the ringing SLIC. The HC55171 trapezoidal ringing application circuit will operate for loop lengths ranging from 0 to 500. In addition, one
Sinusoidal Ringing
The HC55171 uses the same sinusoidal application circuit as the HC5517. The only difference being the values of three components in the ring trip filter. The following table lists the components and the different values required by each device. All reference designators refer to the application
72
HC55171
set of component values will satisfy the entire ringing loop range of the SLIC. A single resistor sets the open circuit RMS ringing voltage, which will set the crest factor of the ringing waveform. The crest factor of the HC55171 ringing waveform is independent of the ringing load (REN) and the loop length. Another robust feature of the HC55171 ringing SLIC is the ring trip detector circuit. The suggested values for the ring trip detector circuit cover quite a large range of applications. The assumptions used to design the trapezoidal ringing application circuit are listed below: * * * * * Loop current limit set to 25mA. Impedance matching is set to 600 resistive. 2-wire surge protection is not required. System able to monitor RTD and SHD. Logic ringing signal is used to drive RC trapezoid network.
TABLE 5. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -60V RTRAP 0 740 1129 CF 1.10 1.15 1.20 RMS 48.2 45.6 43.7 RTRAP 1460 1760 2030 CF 1.25 1.30 1.35 RMS 42.0 40.4 38.8
Ringing Voltage Limiting Factors As the load impedance decreases (increasing REN), the feedback used for impedance synthesis slightly attenuates the ringing signal. Another factor that attenuates the ringing signal is the voltage divider formed by the sense resistors and the impedance of the ringing load. As the load impedance decreases, the 100 of sense resistors becomes a larger percentage of the load impedance. If surge protection resistance must be used with the trapezoidal circuit, the loop length performance of the circuit will decrease. The decrease in ringing loop length is caused by the addition of protection resistors in series with the Tip and Ring outputs. The amount of protection resistance that is added will subtract directly from the loop length. For example if 30 protection resistors is used in each of the Tip and Ring leads, the ringing loop length will decrease by a total of 60. Therefore, subtracting 60 from the graphs will provide the reduced loop length data. Lab Measurements The lab measurements of the trapezoidal ringing circuit were made with the crest factor programming resistor set to 0 and the battery voltage set to -80V. The Bellcore suggested REN model was used to simulate the various ringing loads. A resistor in series with the Tip terminal was used to emulate loop length. A logic gate is used to drive the RC shaping network. When the crest factor programming resistor is set to 0, the output impedance of the logic gate results in a 0.8V/ms slewing voltage on CTRAP. Each graph shows the RMS ringing voltage into a fixed REN load versus loop length. The ringing voltage was measured across the test load. Each test also verified proper operation of the ring trip detector. Proper ring trip detector operation is defined as a constant logic high while ringing and on hook and a constant logic low when off hook is detected. The component values in the application circuit provide a ring trip response in the 100ms to 150ms range.
Crest Factor Programming As previously mentioned, a single resistor is required to set the crest factor of the trapezoidal waveform. The only design variable in determining the crest factor is the battery voltage. The battery voltage limits the peak signal swing and therefore directly determines the crest factor. A set of tables will be provided to allow selection of the crest factor setting resistor. The tables will include crest factors below the Bellcore minimum of 1.2 since many ringing SLIC applications are not constrained by Bellcore requirements.
TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -80V RTRAP 0 389 640 CF 1.10 1.15 1.20 RMS 65.0 62.6 60.0 RTRAP 825 964 1095 CF 1.25 1.30 1.35 RMS 57.6 55.4 53.3
The RMS voltage listed in the table is the open circuit RMS voltage generated by the SLIC.
TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -75V RTRAP 0 500 791 CF 1.10 1.15 1.20 RMS 60.9 58.3 55.9 RTRAP 1010 1190 1334 CF 1.25 1.30 1.35 RMS 53.7 51.6 49.7
TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR VBAT = -65V RTRAP 0 660 1040 CF 1.10 1.15 1.20 RMS 52.5 49.8 47.8 RTRAP 1330 1600 1800 CF 1.25 1.30 1.35 RMS 45.9 44.1 42.5
73
HC55171
55
60 RMS RINGING VOLTAGE
RMS RINGING VOLTAGE
59
52
58
49
46
57
43
56
0 0 100 200 300 400 500 LOOP IMPEDANCE
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 14. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 4 FIGURE 11. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 1
56 58
RMS RINGING VOLTAGE
52
RMS RINGING VOLTAGE
56
48
54
44
52
40
50 0 0 100 200 300 400 500 100 200 300 400 500
LOOP IMPEDANCE
LOOP IMPEDANCE
FIGURE 15. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 5
FIGURE 12. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 2
58
Low Level Ringing Interface The trapezoidal application circuit only requires a cadenced logic signal applied to the wave shaping RC network to achieve ringing. When not ringing, the logic signal should be held low. When the logic signal is low, Tip will be near ground and Ring will be near battery. When the logic signal is high, Tip will be near battery and Ring will be near ground.
RMS RINGING VOLTAGE
55
52
49
46
0
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 13. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 3
74
HC55171
Loop Detector Interface The RTD output should be monitored for off hook detection during the ringing period. At all other times, the SHD should be monitored for off hook detection. The application circuit can be modified to redirect the ring trip information through the SHD interface. The change can be made by rewiring the application circuit, adding a pullup resistor to pin 23 and setting F0 low for the entire duration of the ringing period. The modifications to the application circuit for the single detector interface are shown in Figure 16.
HC55171 ADDITIONAL PULL UP RESISTOR
Tip-to-Ring Open Circuit Voltage The tip-to-ring open-circuit voltage, VOC, of the HC55171 may be programmed to meet a variety of applications. The design of the HC5517 defaults the value of VOC to:
V OC V BAT - 8
NU 23 RDI 20 RDO 21 VRING 24 DTRAP
VCC
Using a zener diode clamping circuit, the default open circuit voltage of the SLIC may be defeated. Some applications that have to meet Maintenance Termination Unit (MTU) compliance have a few options with the HC55171. One option is to reduce the ringing battery voltage until MTU compliance is achieved. Another option is to use a zener clamping circuit on VREF to over ride the default open circuit voltage when operating from a high battery. If a clamping network is used it is important that it is disabled during ringing. The clamping network must be disabled to allow the SLIC to achieve its full ringing capability. A zener clamping circuit is provided in Figure 18.
RTRAP VRING CTRAP
HC55171
FIGURE 16. APPLICATION CIRCUIT WIRING FOR SINGLE LOOP DETECTOR INTERFACE
CIL VREF 3 +5V 47k 2N2907 EN
SLIC Operating State During Ringing The SLIC control pin F1 should always be a logic high during ringing. The control pin F0 will either be a constant logic high (two detector interface) or a logic low (single detector interface). Figure 17 shows the control interface for the dual detector interface and the single detector interface.
FIGURE 18. ZENER CLAMP CIRCUIT WITH DISABLE
Additional Application Information
(DUAL DETECTOR INTERFACE) MODE ACTIVE (LOGIC HI) F1 F0 VRING VALID DET SHD RTD SHD (LOGIC HI) RINGING ACTIVE
The following equations are used to predict the DC output of the ring feed amplifier when using the zener clamping network, VRDC.
V BAT -------------- < V Z 2 V BAT -------------- V Z 2 V BAT V RDC = 2 -------------- + 4 2 V RDC = 2 ( - V Z + ( V CE - V BE ) ) + 4 (EQ. 33)
(EQ. 34)
Where VZ is the zener diode voltage and VCE and VBE are the saturation voltages of the pnp transistor. Using Equations 31 and 32, the tip-to-ring open-circuit voltage can be calculated for any value of zener diode and battery voltage.
V BAT -------------- < V Z 2
ACTIVE
(SINGLE DETECTOR INTERFACE) MODE ACTIVE (LOGIC HI) F1 F0 VRING VALID DET SHD SHD SHD (LOGIC HI) RINGING
V BAT V OC = V TDC - 2 -------------- - 4 2
(EQ. 35)
V BAT -------------- V Z 2
V OC = V TDC - 2 ( - V Z + ( V CE - V BE ) ) - 4 (EQ. 36)
When the base of the pnp transistor is pulled high (+5V), the transistor is off and the zener clamp is disabled. When the base of the transistor is pulled low (0V) the transistor is on and the zener will clamp as long as half the battery voltage is greater than the zener voltage.
FIGURE 17. DETECTOR LOGIC INTERFACES
75
HC55171
Polarity Reversal The HC55171 supports applications that use polarity reversal outside the speech phase of a call connection. The most common implementation of this type of polarity reversal is used with pay phones. By reversing the polarity of the tip and ring terminals of a pay phone, DC current changes direction in a solenoid and the coins are released from the phone. To reverse the polarity of the HC55171, simply toggle the VRING input high. Setting the VRING input high will cause Tip and Ring to reverse polarity. Transhybrid Balance Since the receive signal and its echo are 180 degrees out of phase, the summing node of an operational amplifier can be used to cancel the echo. Nearly all CODECs have an internal amplifier for echo cancellation. The following Figure 19 shows the cancellation amplifier circuit.
RA VRX RB VOUT1 RF
The DC reference from the CODEC is used to bias the analog signals between +5V and ground. The capacitors are required so that the DC gain is unity for proper biasing from the CODEC reference. Also, the capacitors block DC signals that may interfere with SLIC or CODEC operation.
Layout Guidelines and Considerations
The printed circuit board trace length to all high impedance nodes should be kept as short as possible. Minimizing length will reduce the risk of noise or other unwanted signal pickup. The short lead length also applies to all high gain inputs. The set of circuit nodes that can be categorized as such are: * * * * VRX pin 27, the 4-wire voice input. -IN1 pin 13, the inverting input of the internal amplifier. VREF pin 3, the noninverting input to ring feed amplifier. VRING pin 24, the 20V/V input for the ringing signal.
-
+
VO
For multi layer boards, the traces connected to tip should not cross the traces connected to ring. Since they will be carrying high voltages, and could be subject to lightning or surge depending on the application, using a larger than minimum trace width is advised. The 4-wire transmit and receive signal paths should not cross. The receive path is any trace associated with the VRX input and the transmit path is any trace associated with VTX output. The physical distance between the two signal paths should be maximized to reduce crosstalk. The mode control signals and detector outputs should be routed away from the analog circuitry. Though the digital signals are nearly static, care should be taken to minimize coupling of the sharp digital edges to the analog signals. The part has two ground pins, one is labeled AGND and the other BGND. Both pins should be connected together as close as possible to the SLIC. If a ground plane is available, then both AGND and BGND should be connected directly to the ground plane. A ground plane that provides a low impedance return path for the supply currents should be used. A ground plane provides isolation between analog and digital signals. If the layout density does not accommodate a ground plane, a single point grounding scheme should be used.
CODEC VRX RX OUT RA RF RB + TX IN VOUT1 HC55171 +2.5V + -
FIGURE 19. TRANHYBRID AMPLIFIER CIRCUIT
When the SLIC is matched to a 600 load, the echo amplitude is 1/3 the receive input amplitude. Therefore, by configuring the transhybrid amplifier with a gain of 3 in the echo path, cancellation can be achieved. The following equations:
R F R F V O = - V RX ------- + V OUT1 ------- R A R B (EQ. 37)
Substituting the fact that VOUT1 is -1/3 of VRX
R F 1 R F V O = - V RX ------- - V RX -- ------- 3 R R A B (EQ. 38)
Since cancellation implies that under these conditions, the output VO should be zero, set Equation 37 equal to zero and solve for RB.
RA R B = ------3 (EQ. 39)
Another outcome of the transhybrid gain selection is the 2wire to 4-wire gain of the SLIC as seen by the CODEC. The 1/3 voltage gain in the transmit path is relevant to the receive input as well as any signals from the 2-wire side. Therefore by setting the VOUT1 gain to three in the previous analysis, the 2-wire to 4-wire gain was set to unity. Single Supply Codec Interface The majority of CODECs that interface to the ringing SLIC operate from a single +5V supply and ground. Figure 20 shows the circuitry required to properly interface the ringing SLIC to the single supply CODEC. The CODEC signal names may vary from different manufacturers, but the function provided will be the same.
FIGURE 20. SINGLE SUPPLY CODEC INTERFACE
76
HC55171 Pin Descriptions
PLCC 1 2 3 4 SYMBOL AGND VCC VREF F1 DESCRIPTION Analog Ground - Serves as a reference for the transmit output and receive input terminals. Positive Voltage Source - Most Positive Supply. An external voltage connected to this pin will override the internal VBAT/2 reference. Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will ramp close to the output voltage of the tip amplifier. TTL compatible logic control input that must be tied high for proper SLIC operation. TTL compatible logic control input that must be tied high for proper SLIC operation. Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition. Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is ringing. A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller. A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die temperature has been exceeded. Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions. The analog output of the spare operational amplifier. The inverting analog input of the spare operational amplifier. The non-inverting input is internally connected to AGND. An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions with the RING terminal to receive voice signals and for loop monitoring purpose. An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions with the TIP terminal to receive voice signals and for loop monitoring purposes. This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation. Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers deferentially. Not used in this application.This pin should be left floating. Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary. TTL compatible input to drive the uncommitted relay driver. This is the output of the uncommitted relay driver. Battery Ground - All loop current and some quiescent current flows into this terminal. Not used in this application. This pin should be either grounded or left floating. Ring signal input. This is the output of the tip amplifier. This is the output of the ring amplifier. The negative battery source. Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.
5 6 7 8
F0 RS SHD RTD
9
TST
10
ALM
11 12 13 14
ILMT OUT1 -IN1 TIP SENSE
15
RING SENSE 1
16 17
RING SENSE 2 VRX NU VTX RDI RDO BGND NU VRING TF RF VBAT RTI
18 19
20 21 22 23 24 25 26 27 28
77
HC55171 Pinouts
HC55171 (PLCC) TOP VIEW
AGND VREF VBAT VCC RTI RF F1 AGND 1 VCC 2 VREF 3 F0 RS SHD RTD TST ALM 5 6 7 8 9 10 25 TF 24 VRING 23 NU 22 BGND 21 RDO 20 RDI 19 12 OUT 1 13 -IN 1 14 TIP SENSE 15 RING SENSE 1 16 RING SENSE 2 17 VRX 18 NU VTX F1 4 F0 5 RS 6 SHD 7 RTD 8 TST 9 ALM 10 ILMT 11 ILMT 11 OUT 1 12 -IN 1 13 TIP SENSE 14
HC55171 (SOIC) TOP VIEW
28 RTI 27 VBAT 26 RF 25 TF 24 VRING 23 NU 22 BGND 21 RDO 20 RDI 19 VTX 18 NU 17 VRX 16 RING SENSE 2 15 RING SENSE 1
4
3
2
1
28
27
26
Trapezoidal Ringing Application Circuit
U1
HC55171
TIP 14 TIP SENSE RS1 25 TF ILIMT 11 26 RF 16 RING SENSE 2 RS2 RING 15 RING SENSE 1 -IN1 13 RZO OUT1 12 VCC CPS1 CPS2 VBAT 27 VBAT VRING 24 CIL VREF 3 F1 F0 VCC TST 4 F1 5 F0 6 RS 9 TST 20 RDI SHD 7 RTD 8 ALM 10 SHD RTD ALM DTRAP CTRAP RTRAP VRING 2 VCC 1 AGND 22 BGND RTI 28 RRT3 CRT DRT RRT2 RRT1 V-XMIT VTX 19 CAC RRF CRX VRX 17 RIL2 RIL1 V-REC
FIGURE 21. TRAPEZOIDAL RINGING APPLICATION CIRCUIT
78
HC55171 HC55171 Trapezoidal Ringing Application Circuit Parts List
COMPONENT U1 - Ringing Slic RS1, RS2 RZO, RIL1 RRT1 RRT2 RRT3 RRF VALUE HC55171 49.9 56.2k 49.9k 1.5M 51.1k 45.3k TOLERANCE N/A 1% 1% 1% 1% 1% 1% RATING N/A 1/2W 1/8W 1/8W 1/8W 1/8W 1/8W COMPONENT RIL2 RTRAP CPS1, CPS2 CIL, CRT, CAC, CRX CTRAP DRT, DTRAP VALUE 7.68k App Driven 0.1F 0.47F 4.7F 1N914 TOLERANCE 1% 1% 10% 10% 10% RATING 1/8W 1/8W 100V 50V 10V
Generic Rectifier Diode
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